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MPC105/d (motorola order number) 1/95 rev 1 this document contains information on a new product under development. speci?cations and information herein are subject to chan ge without notice. motorola inc. 1995 ? powerpc, powerpc architecture, and powerpc 604 are trademarks of international business machines corp. used by motorola under l icense from ibm corp. MPC105 technical summary advance information MPC105 pci bridge/memory controller technical summary this document provides an overview of the MPC105 pci bridge/memory controller (pcib/mc). it includes the following: ? an overview of MPC105 features ? details about the MPC105 device. this includes descriptions of the MPC105s functional units and interfaces. ? a description of the MPC105s signals and registers in this document, the term 60x is used to denote a 32-bit microprocessor from the powerpc architecture ? family. 60x processors implement the powerpc ? architecture as it is speci?ed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits, and ?oating-point data types of 32 and 64 bits (single-precision and double-precision). 1.1 overview the MPC105 provides a powerpc reference platform compliant bridge between the powerpc microprocessor family and the peripheral component interconnect (pci) bus. pci support allows system designers to rapidly design systems using peripherals already designed for pci and the other standard interfaces available in the personal computer hardware environment. the MPC105 integrates secondary cache control and a high- performance memory controller that supports dram, sdram, rom, and flash rom.
2 MPC105 pci bridge/memory controller technical summary the MPC105 is the ?rst device in a family of products that provides system-level support for industry- standard interfaces to be used with powerpc microprocessors. the MPC105 uses an advanced, 3.3 v cmos process technology and is fully compatible with ttl devices. this document describes the MPC105, its interfaces and its signals. 1.2 MPC105 pcib/mc features the MPC105 provides an integrated high bandwidth, high performance, ttl-compatible interface between a 60x processor, a secondary (l2) cache or secondary 60x processor, the pci bus, and main memory. this section summarizes the features of the MPC105 and provides a block diagram showing the major functional units. figure 1 shows the MPC105 in a typical system implementation. the major functional units within the MPC105 are also shown in figure 1. note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device. figure 1. system implementation and block diagram memory (dram, sdram, rom, flash rom) l2 cache interface 60x interface memory interface pci interface jtag interface interrupt director power support management 60x processor MPC105 l2 cache or secondary 60x processor buffers 60x data 60x address 60x control pci address/data pci control control control address
MPC105 pci bridge/memory controller technical summary 3 major features of the MPC105 are as follows: ? processor interface 60x processors supported at a wide range of frequencies 32-bit address bus con?gurable 64- or 32-bit data bus accommodates an upgrade of either an external l2 cache or a secondary processor arbitration for secondary processor on-chip full memory coherency supported pipelining of 60x accesses store gathering on 60x to pci writes ? secondary (l2) cache control con?gurable for write-through or write-back operation 256k, 512k, 1m sizes up to 4 gbytes of cacheable space direct-mapped parity supported supports external byte decode or on-chip byte decode for write enables programmable timing supported synchronous burst and asynchronous srams supported ? pci interface compliant with pci local bus speci?cation, revision 2.0 supports pci interlocked accesses to memory using lock signal and protocol supports accesses to all pci address spaces selectable big- or little-endian operation store gathering on pci writes to memory selectable memory prefetching of pci read accesses only one external load presented by the MPC105 to the pci bus pci con?guration registers interface operates at 20C33 mhz data buffering (in/out) parity supported 3.3 v/5.0 v-compatible ? concurrent transactions on 60x and pci buses supported ? memory interface programmable timing supported supports either dram or synchronous dram (sdram) high bandwidth (64-bit) data bus supports self-refreshing dram in sleep and suspend modes supports 1 to 8 banks built of x1, x4, x8, x9, x16, or x18 drams supports powerpc reference platform compliant contiguous or discontiguous memory maps 1 gbyte of ram space, 16 mbytes of rom space supports 8-bit asynchronous rom or 32-/64-bit burst-mode rom
4 MPC105 pci bridge/memory controller technical summary supports writing to flash rom con?gurable external buffer control logic parity supported ttl compatible ? power management fully-static 3.3 v cmos design supports 60x nap, doze, and sleep power management modes, and suspend mode ? ieee 1149.1-compliant, jtag boundary scan interface ? 304-pin ball grid array (bga) package 1.3 MPC105 major functional units the MPC105 consists of the following major functional units: ? 60x processor interface ? secondary (l2) cache/processor interface ? pci interface ? memory interface this section describes each of these functional units. 1.3.1 60x processor interface the MPC105 supports a programmable interface to a variety of powerpc microprocessors operating at various bus speeds. the 60x processor interface uses a subset of the 60x bus protocol, which enables the interface between the processor and MPC105 to be optimized for performance. depending on the system implementation, the processor may operate at the pci bus clock rate, or at two or three times the pci bus clock rate. the bus is synchronous, with all timing relative to the rising edge of the bus clock. inputs are sampled at, and outputs are driven from, this edge. the address bus is 32 bits wide and the data bus is 64 bits wide (or 32 bits in 32-bit mode). the MPC105 supports single-beat and burst data transfers. the processor interface has decoupled address and data buses to support pipelined transactions. pci bus accesses to the system memory space are passed to the 60x processor(s) and/or l2 cache for snooping purposes. 1.3.2 secondary (l2) cache/processor interface the MPC105s 60x interface allows for a variety of system con?gurations by providing support for either a direct-mapped, lookaside, l2 cache or a secondary 60x processor. the MPC105 uses snoop operations to ensure data coherency between the caches (one or two l1 caches, or one l1 and one l2) and main memory. the l2 cache interface generates the arbitration and support signals necessary to maintain a write-through or write-back l2 cache. the l2 cache interface supports either burst srams or asynchronous srams, and l2 data parity on a per-byte basis. the MPC105 features on-chip byte decoding for l2 data write enables or can be con?gured to use external logic for data write enable generation.
MPC105 pci bridge/memory controller technical summary 5 the l2 cache interface handles the following types of bus cycles: ? normal 60x bus cycles ? 60x internal cache copy-back cycles ? l2 copy-back cycles ? snoop cycles when a secondary 60x processor is used instead of an l2 cache, three signals (dir ty_in/br1 , dir ty_out/bg1 , and t oe/dbg1 ) change their functions to allow for arbitration between two 60x processors. excepting the bus request, bus grant, and data bus grant signals, all other 60x interface signals are shared by both 60x processors. 1.3.3 pci interface the pci interface connects the processor and memory buses to the pci bus, to which i/o components are connected, without the need for glue logic. this interface acts as both a master and slave device. the pci interface supports a 32-bit multiplexed, address/data bus that can operate from 20 mhz to 33 mhz. buffers are provided for i/o operations between the pci bus and the 60x processor or memory. processor read and write operations each have a 32-byte buffer, and memory operations have one 32-byte read buffer and two 32-byte write buffers. the pci interface supports address and data parity with error checking and reporting. the interface also supports three physical address spaces32-bit address memory, 32-bit address i/o, and some of the pci 256-byte con?guration space. mode selectable big-endian to little-endian conversion is also supplied at the pci interface. the MPC105s pci interface is compliant with the pci local bus speci?cation, revision 2.0, and follows the guidelines in the pci system design guide, revision 1.0 for host bridge architecture. 1.3.4 memory interface the memory interface controls processor and pci interactions to main memory. it is capable of supporting a variety of dram or sdram, and rom or flash rom con?gurations as main memory. the maximum supported memory size is 1 gbyte of dram or sdram, with 16 mbytes of rom or 1 mbyte of flash rom. the MPC105 con?gures its memory control to support the various memory sizes through software initialization of on-chip con?guration registers. parity protection is provided for the dram or sdram. if sdram is used, it must comply with the jedec speci?cation for sdram. the MPC105 can control either a 64- or 32-bit data path to main memory; sdram systems support 64-bit data paths only. to reduce loading on the data bus, system designers may implement buffers between the 60x bus and memory. the MPC105 features con?gurable data buffer control logic to accommodate several buffer types. the MPC105 handles parity checking and generation, with four parity bits checked or generated for a 32-bit data path, and eight parity bits checked or generated for a 64-bit data path. the MPC105 is capable of supporting a variety of dram or sdram con?gurations. twelve multiplexed address signals provide for device densities to 16 m. eight row address strobe/command select ( ras/cs ) signals support up to eight banks of memory. each bank can be 8 bytes wide. eight column address strobe/ data quali?er ( cas/dqm ) signals are used to provide byte selection for memory accesses. dram or sdram banks can be built of simms or directly attached memory chips. the data path to the memory banks must be either 32 or 64 bits wide (36 or 72 with parity). the banks can be constructed using x1, x4, x8, x9, x16, or x18 memory chips. regardless of whether drams or sdrams are used, the memory design must be byte-selectable for writes using the cas/dqm signals.
6 MPC105 pci bridge/memory controller technical summary the MPC105 memory interface provides for doze, nap, sleep, and suspend power saving modes, de?ned in section 1.4, power management. in the sleep and suspend power saving modes, the MPC105 can be con?gured to put the dram array into a self-refresh mode, (if supported by the drams). the MPC105 may be con?gured to use the rtc input as its refresh time base in suspend mode. if self-refreshing drams are not available or the rtc input is not used (in suspend mode), system software must preserve dram data (such as by copying the data to disk) in the sleep or suspend mode. in the doze and nap power saving modes and in the full-on mode, the MPC105 supplies cas before ras (cbr) refresh to dram. an MPC105 con?guration signal (sampled at reset) determines whether the MPC105 accesses boot code from rom or flash rom. if the MPC105 is con?gured to access boot code from rom, the corresponding data path must be the same bit width as the dram or sdram data path (32 or 64 bits). twenty address bits and two bank selects are provided for rom systems. if the MPC105 is con?gured to access boot code from flash rom, the corresponding data path must be 8 bits wide and must be connected to the most signi?cant byte of the data bus. twenty address bits, one bank select signal, one write enable signal, and one output enable signal are provided for flash rom systems. 1.4 power management the MPC105 provides hardware support for four levels of power reduction; the doze, nap, and sleep modes are invoked by register programming, and the suspend mode is invoked by assertion of an external signal. the design of the MPC105 is fully static, allowing internal logic states to be preserved during all power saving modes. the following sections describe the programmable power modes provided by the MPC105. 1.4.1 full-on mode this is the default power state of the MPC105 following a hard reset, with all internal functional units fully powered and operating at full clock speed. 1.4.2 doze mode in this power saving mode, all the MPC105 functional units are disabled except for pci address decoding, system ram refreshing, and the cpu bus request monitoring (through brx ). once the doze mode is entered, a hard reset, a pci transaction referenced to the system memory, or a bus request can bring the MPC105 out of the doze mode and into the full-on state. if the MPC105 is awakened for a processor or pci bus access, the access is completed and the MPC105 returns to the doze mode. the MPC105s doze mode is totally independent of the power saving mode of the processor. 1.4.3 nap mode further power savings can be achieved through the nap mode, when both the processor and the MPC105 are placed in a power reduction mode. in this mode, only the pci address decoding, system ram refresh, and the processor bus request monitoring are still operating. hard reset, a pci bus transaction referenced to the system memory, or a bus request can bring the MPC105 out of the nap mode. if the MPC105 is awakened by a pci access, the access is completed, and the MPC105 returns to the nap mode. if the MPC105 is awakened by a processor access, the access is completed, but the MPC105 remains in the full- on state. when in the nap mode, the pll is required to be running and locked to the system clock (sysclk).
MPC105 pci bridge/memory controller technical summary 7 1.4.4 sleep mode sleep mode provides further power savings compared to the nap mode. as in nap mode, both the processor and the MPC105 are placed in a reduced power mode concurrently. in sleep mode, no functional units are operating except the system ram refresh logic, which can continue (optionally) to perform the refresh cycles. a hard reset or a bus request wakes the MPC105 from the sleep mode. the pll and sysclk inputs may be disabled by an external power management controller (pmc). for additional power savings, the pll can be disabled by con?guring the pll0Cpll3 signals into the pll bypass mode. when recovering from sleep mode, the external pmc has to re-enable the pll and sysclk first, and then wake up the system after allowing the pll time to relock. 1.4.5 suspend mode suspend mode is activated through assertion of the suspend signal. in suspend mode, the MPC105 may have its clock input and pll shut down for additional power savings. memory refresh can be accomplished in two wayseither by using self-refresh mode drams or by using the rtc input. to exit the suspend mode, the system clock must be turned on in suf?cient time to restart the pll. after this time, suspend may be negated. in suspend mode, all outputs (except memory refresh) are high impedance and all inputs (including hrst ) are ignored. 1.5 signals the MPC105s signals, shown in figure 2, are grouped as follows: ? 60x processor interface signals ? secondary cache/processor interface signals ? pci interface signals ? memory interface signals ? interrupt, clock, and power management signals ? ieee 1149.1 interface signals ? con?guration signals note a bar over a signal name indicates that the signal is active lowfor example, ar tr y (address retry) and ts (transfer start). active-low signals are referred to as asserted (active) when they are low and negated when they are high. signals that are not active low, such as par (pci bus parity signal) and tt0Ctt4 (transfer type signals) are referred to as asserted when they are high and negated when they are low.
8 MPC105 pci bridge/memory controller technical summary figure 2. MPC105 signal groupings 8 ad31Cad0 frame irdy lock devsel ma0Cma11/ar8Car19 cas/dqm0 Ccas/dqm7 we sdras , sdcas /ele cke /dwe7 rtc 12 8 1 2 1 1 1 32 1 1 1 1 1 memory interrupt, pci trdy 2 serr , perr flshreq 1 st op 1 c/be3 Cc/be0 par 4 1 mcp 1 qreq 1 rcs0 1 bctl0 , bctl1 2 ras/cs0 Cras/cs7 8 1 1 isa_master foe/rcs1 par0Cpar7/ar0Car7 baa /ba1 1 doe 1 hit 1 secondary br0 tt0Ctt4 a0Ca31 tbst aack 1 1 5 32 1 1 60x xa ts 3 wt , ci , gbl ar tr y 1 tsiz0Ctsiz2 3 bg0 ts 1 1 dbg0 1 tea 1 t a 64 dh0Cdh31, dl0Cdl31 data req 1 gnt 1 1 nmi, hrst 2 1 sysclk 1 memack 1 1 1 1 1 ads /dale tale/ba0 dir ty_in/br1 dir ty_out/bg1 t oe/dbg1 1 tdo cko/ dwe3 qack suspend 1 1 t aloe twe tv 1 1 1 dwe 0 Cdwe7 8 ieee 1149.1 tck tms trst 1 1 1 1 tdi processor interface cache/ processor interface interface interface jtag interface clock, and power management signals
MPC105 pci bridge/memory controller technical summary 9 1.5.1 60x processor interface signals table 1 lists the 60x processor interface signals on the MPC105 and provides a brief description of their functions. table 1. 60x processor interface signals signal signal name number of pins i/o signal description br0 bus request 0 1 i indicates that the primary 60x requires the bus for a transaction bg0 bus grant 0 1 o indicates that the primary 60x may, with the proper quali?cation, begin a bus transaction and assume mastership of the address bus ts transfer start 1 o indicates that the MPC105 has started a bus transaction, and that the address and transfer attribute signals are valid. note that the MPC105 only initiates a transaction to broadcast the address of a pci access to memory for snooping purposes. i indicates that a 60x bus master has begun a transaction, and that the address and transfer attribute signals are valid xa ts extended address transfer start 1 i indicates that the 60x has started a direct-store access (using the extended transfer protocol). since direct-store accesses are not supported by the MPC105, the MPC105 automatically asserts tea when xa ts is asserted (provided tea is enabled). a0Ca31 address bus 32 o speci?es the physical address for 60x bus snooping or for an l2 copy-back operation i speci?es the physical address of the bus transaction. for burst reads, the address is aligned to the critical double-word address that missed in the instruction or data cache. for burst writes, the address is aligned to the double-word address of the cache line being pushed from the data cache. tt0Ctt4 transfer type 5 o speci?es the type of 60x bus transfer in progress for snooping i speci?es the type of 60x bus transfer in progress tsiz0Ctsiz2 transfer size 3 o speci?es the data transfer size for the 60x bus transaction i speci?es the data transfer size for the 60x bus transaction tbst transfer burst 1 o indicates that a burst transfer is in progress i indicates that a burst transfer is in progress
10 MPC105 pci bridge/memory controller technical summary aack address acknowledge 1 o indicates that the address tenure of a transaction is terminated. on the cycle following the assertion of aack , the bus master releases the address-tenure-related signals to a high impedance state and samples ar tr y . i indicates that a 60x bus slave is terminating the address tenure. on the cycle following the assertion of aack , the bus master releases the address tenure related signals to a high impedance state and samples ar tr y . ar tr y address retry 1 o indicates that the initiating 60x bus master must retry the current address tenure i during a snoop operation, indicates that the 60x either requires the current address tenure to be retried due to a pipeline collision or needs to perform a snoop copy-back. during normal 60x bus cycles in a multiprocessor system, indicates that the other 60x requires the address tenure to be retried. dbg0 data bus grant 0 1 o indicates that the 60x may, with the proper quali?cation, assume mastership of the data bus. a quali?ed data bus grant is the assertion of bg0 , negation of dbb , and negation of ar tr y . the address retry (ar tr y ) is only for the address bus tenure associated with the data bus tenure about to be granted (that is, not for another address tenure available because of address pipelining). dh0Cdh31, dl0Cdl31 data bus 64 the data bus is comprised of two halvesdata bus high (dh) and data bus low (dl). the data bus has the following byte lane assignments: data byte byte lane dh0Cdh7 0 dh8Cdh15 1 dh16Cdh23 2 dh24Cdh31 3 dl0Cdl7 4 dl8Cdl15 5 dl16Cdl23 6 dl24Cdl31 7 o represents the value of data during a processor- read-from-pci transaction, a pci-write-to- memory transaction, or when the MPC105 ?ushes the l2 copy-back buffer i represents the state of data during a processor- write-to-pci transaction, a pci-read-from- memory transaction, or when the l2 is loading the copy-back buffer table 1. 60x processor interface signals (continued) signal signal name number of pins i/o signal description
MPC105 pci bridge/memory controller technical summary 11 1.5.2 secondary cache/processor interface signals the MPC105 provides support for either a secondary lookaside l2 cache or an additional 60x processor. 1.5.2.1 secondary cache (l2) interface signals table 2 lists the secondary cache interface signals and provides a brief description of their functions. the l2 cache interface supports either burst srams or asynchronous srams. some of the l2 interface signals perform different functions depending on the sram con?guration and whether the on-chip byte decode logic is enabled. ci cache inhibit 1 i/o indicates that an access is caching-inhibited wt write through 1 i/o indicates that an access is write-through gbl global 1 i/o indicates that an access is global (that is, coherency needs to be enforced by hardware) t a transfer acknowledge 1 o indicates that the data has been latched for a write, or that the data is valid for a read, thus terminating the current data beat. if it is the last or only data beat, this also terminates the data tenure. i indicates that a 60x bus slave has latched data for a write operation, or is indicating the data is valid for a read operation. if it is the last or only data beat, then the data tenure is terminated. tea transfer error acknowledge 1 o indicates that a bus error has occurred. assertion of tea terminates the transaction in progress; that is, it is not necessary to assert t a because it will be ignored by the target processor. an unsupported memory transaction, such as a direct-store access or a graphics read or write, will cause the assertion of tea (provided tea is enabled). table 1. 60x processor interface signals (continued) signal signal name number of pins i/o signal description
12 MPC105 pci bridge/memory controller technical summary table 2. secondary cache interface signals signal signal name number of pins i/o signal description ads /dale address strobe/ data address latch enable 1 o for a burst sram con?guration, indicates to the burst sram that the address is valid to be latched CorC for an asynchronous sram con?guration, indicates to the external address latch that the address is valid to be latched baa /ba1 bus address advance/burst address 1 1 o for a burst sram con?guration, indicates that the burst rams should increment their internal addresses CorC for an asynchronous sram con?guration, indicates the least signi?cant bit of the burst address dir ty_in/br1 dirty in 1 i indicates that the selected l2 cache line is modi?ed. the polarity of dir ty_in/br1 is programmable. dir ty_out/bg1 dirty out 1 o indicates that the l2 cache line should be marked as modi?ed. the polarity of dir ty_out/bg1 is programmable. doe data ram output enable 1 o indicates that the l2 data rams should drive the data bus hit hit 1 i indicates that the l2 cache has detected a hit. the polarity of hit is programmable. tale/ba0 tag address latch enable/ burst address 0 1 o for a burst sram con?guration, indicates that the address latch should be in the transparent state for the l2 local address bus CorC for an asynchronous sram con?guration, indicates the most signi?cant bit of the burst address t aloe tag address latch output enable 1 o indicates that the address latch should drive the l2 local address bus for tag lookup or tag write t oe /dbg1 tag output enable 1 o indicates that the tag ram should drive the l2 tag address onto the address bus twe tag write enable 1 o indicates that the l2 tag address, valid, and dirty bits should be updated
MPC105 pci bridge/memory controller technical summary 13 1.5.2.2 secondary processor signals when a secondary 60x processor is used instead of an l2 cache, three signals change their functions. table 3 lists the secondary processor interface signals and provides a brief description of their functions. 1.5.3 pci interface signals table 4 lists the pci interface signals and provides a brief description of their functions. note that the bits in table 4 are referenced in little-endian format. the pci speci?cation de?nes a sideband signal as any signal, not part of the pci speci?cation, that connects two or more pci-compliant agents, and has meaning only to those agents. the MPC105 implements three pci sideband signals isa_master , flshreq , and memack . tv tag valid 1 o indicates that the current l2 cache line should be marked valid. the polarity of tv is programmable. fnr/ dwe0 , dwe/dwe1 , dwe2 , cko/ dwe3 , dwe4 Cdwe6 , cke/dwe7 data ram write enable (dwe0 Cdwe7 ) 8 o for external byte decode con?gurations, dwe/ dwe1 indicates that a write to the l2 data rams is in progress CorC for on-chip byte decode con?gurations, dwe0 C dwe7 function as individual byte lane (0C7) write enables for the l2 data rams table 3. secondary processor interface signals signal signal name number of pins i/o signal description dir ty_in/br1 bus request 1 1 i indicates that the secondary processor requires mastership of the 60x bus for a transaction dir ty_out/bg1 bus grant 1 1 o indicates that the secondary processor may, with the proper quali?cation, begin a 60x bus transaction and assume mastership of the address bus t oe /dbg1 data bus grant 1 1 o indicates that the secondary processor may, with the proper quali?cation, assume mastership of the 60x data bus table 2. secondary cache interface signals (continued) signal signal name number of pins i/o signal description
14 MPC105 pci bridge/memory controller technical summary table 4. pci bus interface signals signal signal name number of pins i/o signal description ad31Cad0 address/data 32 o represents the physical address during the ?rst clock of a transaction. during subsequent clocks, ad31Cad0 contain data being written. ad7Cad0 de?ne the least signi?cant byte and ad31Cad24 the most signi?cant byte. i represents the address to be decoded as check for device select or data being received c/be3 Cc/be0 command/byte enables 4 o during the address phase, c/be3 Cc/be0 de?ne the bus command. during the data phase, c/be3 Cc/be0 are used as byte enables. byte enables determine which byte lanes carry meaningful data. c/be0 applies to the least signi?cant byte. i indicates the command that another master is running, or which byte lanes are valid par parity 1 o asserted indicates odd parity across the ad31C ad0 and c/be 3 Cc/be0 signals during address and data phases. negated indicates even parity. i asserted indicates odd parity driven by another pci master or the pci target during read data phases. negated indicates even parity. trdy target ready 1 o indicates that the MPC105, acting as a pci target, can complete the current data phase of a pci transaction. during a read, the MPC105 asserts t rdy to indicate that valid data is present on ad31Cad0. during a write, the MPC105 asserts trdy to indicate that it is prepared to accept data. i indicates another pci target is able to complete the current data phase of a transaction irdy initializer ready 1 o indicates that the MPC105, acting as a pci master, can complete the current data phase of a pci transaction. during a write, the MPC105 asserts irdy to indicate that valid data is present on ad31Cad0. during a read, the MPC105 asserts irdy to indicate that it is prepared to accept data. i indicates another pci master is able to complete the current data phase of the transaction
MPC105 pci bridge/memory controller technical summary 15 frame frame 1 o indicates that the MPC105, acting as a pci master, is initiating a bus transaction. while frame is asserted, data transfers continue. i indicates that another pci master is initiating a bus transaction st op stop 1 o indicates that the MPC105 is requesting that the pci bus master stop the current transaction i indicates that some other pci agent is requesting that the MPC105, acting as the pci master, stop the current transaction lock lock 1 i indicates that a master is requesting exclusive access to memory, which may require multiple transactions to complete devsel device select 1 o indicates that the MPC105 has decoded the address and is the target of the current access i indicates that some pci agent (other than the MPC105) has decoded its address as the target of the current access req pci bus request 1 o indicates that the MPC105 is requesting control of the pci bus. note that req is a point-to-point signal. every master has its own req signal. gnt pci bus grant 1 i indicates that the MPC105 has been granted control of the pci bus. note that gnt is a point- to-point signal. every master has its own gnt signal. serr system error 1 o indicates that an address parity error or some other system error (where the result will be a catastrophic error) was detected i indicates that another target has determined a catastrophic error perr parity error 1 o indicates that the MPC105, acting as a pci target, detected a data parity error i indicates that another target detected a data parity error while the MPC105 was the master isa_master isa master 1 i indicates that an isa master is requesting system memory table 4. pci bus interface signals (continued) signal signal name number of pins i/o signal description
16 MPC105 pci bridge/memory controller technical summary 1.5.4 memory interface signals table 5 lists the memory interface signals and provides a brief description of their functions. the memory interface supports either standard drams or synchronous drams (sdrams), and either standard roms or flash roms. some of the memory interface signals perform different functions depending on the ram and rom con?gurations. flshreq flush request 1 i indicates that a device needs to have the MPC105 ?ush all of its current operations memack flush acknowledge 1 o indicates that the MPC105 has ?ushed all of its current operations and has blocked all 60x transfers except snoop copy-back operations. the MPC105 will assert memack after the ?ush is complete. table 5. memory interface signals signal signal name number of pins i/o signal description ras/cs0 C ras/cs7 row address strobe for dram/ command select for sdram 8 o indicates a dram row address is valid and selects one of the rows in the bank CorC selects an sdram bank to perform a memory operation cas/dqm0 C cas/dqm7 column address strobe/ data quali?er 8 o indicates a dram column address is valid and selects one of the columns in the row. cas/ dqm0 connects to the most signi?cant byte select. cas/dqm7 connects to the least signi?cant byte select. CorC prevents writing to sdram. we write enable 1 o enables writing to dram or flash rom CorC part of sdram command encoding ma0Cma11/ ar8Car19 memory address 0C11/ rom address 8C19 12 o represents the row/column multiplexed physical address for drams or sdrams (ma0 is the most signi?cant address bit; ma11 is the least signi?cant address bit) CorC represents bits 8C19 of the rom or flash rom address (the 12 lowest order bits, with ar19 as the lsb). bits 0C7 of the rom address are provided by par0Cpar7/ar0Car7. table 4. pci bus interface signals (continued) signal signal name number of pins i/o signal description
MPC105 pci bridge/memory controller technical summary 17 par0Cpar7/ ar0Car7 data parity 0C7/ rom address 0C7 8 o represents the byte parity being written to memory (par0 is the most signi?cant parity bit) CorC represents bits 0C7 of the rom or flash rom address (the eight highest order bits, with ar0 as the msb). bits 8C19 of the rom address are provided by ma0Cma11/ar8Car19. i represents the byte parity being read from memory (par0 is the most signi?cant parity bit) cke /dwe7 memory clock enable 1 o enables the internal clock circuit of the sdram memory. also cke/dwe7 is part of the sdram command encoding. note that the MPC105 negates cke /dwe7 during certain system power down situations. sdras row address strobe for sdram 1 o sdras is part of the sdram command encoding used for sdram bank selection during read or write operations sdcas /ele column address strobe for sdram/ external latch enable 1 o sdcas /ele is part of the sdram command encoding used for sdram column selection during read or write operations CorC enables the external data buffer for read operations, if such a buffer is used in the system rcs0 rom/flash rom bank 0 select 1 o selects the ?rst rom bank or flash rom for a read access foe/rcs1 flash rom output enable/ rom second bank select 1 o enables flash rom output for the current read access CorC selects the second rom bank for a read access bctl0 bctl1 buffer control 0, buffer control 1 2 o used to control external data bus buffers (directional control and high-impedance state) between the 60x bus and memory. note that external data buffers may be optional for lightly loaded data buses, but buffers are required whenever an l2 cache and rom/flash rom are both in the system. rtc real-time clock 1 i external clock source for the memory refresh logic when the MPC105 is in the suspend power- saving mode table 5. memory interface signals (continued) signal signal name number of pins i/o signal description
18 MPC105 pci bridge/memory controller technical summary 1.5.5 interrupt, clock, and power management signals the MPC105 coordinates a few miscellaneous signals across the memory bus, the pci bus, and the 60x bus. these include interrupt, clocking, and power management signals. table 6 lists these signals and provides a brief description of their functions. table 6. interrupt, clocking, and power management signals signal signal name number of pins i/o signal description nmi nonmaskable interrupt 1 i indicates that the MPC105 should signal a machine check interrupt to the 60x processor mcp machine check 1 o indicates that the MPC105 detected an illegal transaction, a memory select error, or a parity error on a memory read cycle. assertion of serr , perr , or nmi may also trigger mcp . hrst hard reset 1 i indicates that a complete hard reset must be initiated by the MPC105 (perform circuit initialization followed by a system reset interrupt). during assertion, all bidirectional signals are released to the high impedance state and all output signals are either in a high impedance or inactive state. sysclk system clock 1 i sysclk set the frequency of operation for the pci bus, and provides a reference clock for the phase-locked loops (plls) in the 60x and the MPC105. sysclk is used to synchronize bus operations. refer to section 1.5.8, clocking, for more information. ck0/ dwe3 test clock 1 o this signal provides a means to test or monitor the internal pll output, or the bus clock frequency. the test clock should be used for testing purposes only. it is not intended to be used as a reference clock. qreq quiesce request 1 i indicates that a 60x processor is requesting that all bus activity involving snoop operations pause or terminate so that the 60x processor may enter a low-power state qack quiesce acknowledge 1 o indicates that the MPC105 is in a low-power state. all bus activity that requires snooping has terminated, and the 60x processor may enter a low-power state. suspend suspend 1 i activates the suspend power-saving mode
MPC105 pci bridge/memory controller technical summary 19 1.5.6 ieee 1149.1 interface signals to facilitate system testing, the MPC105 provides a jtag test port that complies with the ieee 1149.1 boundary scan speci?cation. table 7 describes the jtag test port signals. 1.5.7 con?guration signals several of the MPC105 signals are sampled during a power-on reset to determine the con?guration of the rom, flash rom, and dynamic memory, the data-bus width, and the phased-locked loop clock mode. weak pull-up or pull-down resistors should be used so as not to interfere with the normal operation of the signals. table 8 describes the signals sampled during a power-on reset, and how they are con?gured. table 7. ieee 1149.1 boundary scan signals signal signal name number of pins i/o signal description tdo jtag test data output 1 o the contents of the selected internal instruction or data register are shifted out onto this signal on the falling edge of tck. tdo will remain in a high impedance state except when scanning of data is in progress. tdi jtag test data input 1 i the value presented on this signal on the rising edge of tck is clocked into the selected jtag test instruction or data register. tck jtag test clock 1 i this input should be driven by a free-running clock signal. input signals to the test access port (tap) are clocked in on the rising edge of tck. changes to the tap output signals occur on the falling edge of tck. the test logic allows tck to be stopped. tms jtag test mode select 1 i this signal is decoded by the internal jtag tap controller to distinguish the primary operation of the test support circuitry. trst jtag test reset 1 i this input causes asynchronous initialization of the internal jtag tap controller. table 8. power-on configuration signals signal number of pins i/o con?guration fnr/ dwe0 1 i highcon?gures the MPC105 for flash (8-bit interface) memory. lowcon?gures the MPC105 for rom (32- or 64- bit interface) memory rcs0 1 i highindicates rom is located on the 60x processor/ memory data bus lowindicates rom is located on the pci bus
20 MPC105 pci bridge/memory controller technical summary 1.5.8 clocking the MPC105 can be con?gured to operate internally at x1 or x2 of the pci bus clock (sysclk) by using the pll0Cpll3 signals. table 9 shows the clock combinations supported by an MPC105-based system. dl[0] 1 i highcon?gures the MPC105 for 64-bit processor/memory data bus width low con?gures the MPC105 for 32-bit processor/memory data bus width xa ts 1 i highcon?gures the MPC105 for address map a lowcon?gures the MPC105 for address map b pll0Cpll3 4 i high/lowcon?guration for the pll clock mode table 9. clock frequencies 60x processor external clock frequency 60x processor internal clock frequency MPC105 external clock frequency (sysclk) 1 MPC105 internal clock frequency pci bus clock (sysclk) 1 40 mhz 80 mhz 20 mhz 40 mhz 20 mhz 25 mhz 75 mhz 2 25 mhz 25 mhz 25 mhz 33 mhz 66 mhz 33 mhz 33 mhz 33 mhz 33 mhz 100 mhz 33 mhz 33 mhz 33 mhz 66 mhz 66 mhz 33 mhz 66 mhz 33 mhz 66 mhz 100 mhz 3 33 mhz 66 mhz 33 mhz 1 the MPC105 external clock and the pci bus clock are the same signal (sysclk). 2 80 mhz processor operating at 75 mhz. 3 powerpc 604 ? microprocessor only. table 8. power-on configuration signals (continued) signal number of pins i/o con?guration
MPC105 pci bridge/memory controller technical summary 21 1.6 con?guration registers the MPC105 provides user accessible registers for con?guration, initialization, and error handling. these registers are generally set by initialization software following a power-on reset or hard reset, or by error handling routines. table 10 describes the con?guration registers provided by the MPC105. figure 3 shows the registers in the con?guration space of the MPC105. table 10. MPC105 configuration registers address offset register size program accessible size register register access reset value 00 2 bytes 2 bytes vendor id =1057h read 0x1057 02 2 bytes 2 bytes device id = 0001h read 0x0001 04 2 bytes 2 bytes pci command read/write 0x0006 06 2 bytes 2 bytes pci status read/bit-reset 0x0080 08 1 byte 1 byte revision id read 0x nn 09 1 byte 1 byte standard programming interface read 0x00 0a 1 byte 1 byte subclass code read 0x00 0b 1 byte 1 byte class code read 0x06 0c 1 byte 1 byte cache line size read 0x00 0d 1 byte 1 byte latency timer read 0x00 0e 1 byte 1 byte header type read 0x00 0f 1 byte 1 byte bist control read 0x00 3c 1 byte 1 byte interrupt line read 0x00 3d 1 byte 1 byte interrupt pin read 0x00 3e 1 byte 1 byte min gnt read 0x00 3f 1 byte 1 byte max gnt read 0x00 40 1 byte 1 byte bus number read 0x00 41 1 byte 1 byte subordinate bus number read 0x00 42 1 byte 1 byte disconnect counter read 0x00 44 2 bytes 2 bytes special cycle address read 0x0000 70 2 bytes 1 or 2 bytes power management con?guration read/write 0x00 80C87 8 bytes 1, 2, or 4 bytes memory starting address read/write 88C8f 8 bytes 1, 2, or 4 bytes extended memory starting address read/write 90C97 8 bytes 4 bytes memory ending address read/write 98C9f 8 bytes 1, 2, or 4 bytes extended memory ending address read/write
22 MPC105 pci bridge/memory controller technical summary a0 1 byte 1 byte memory enable read/write a8 4 bytes 1, 2, or 4 bytes processor interface con?guration 1 read/write 0xff00_0410 ac 4 bytes 1, 2, or 4 bytes processor interface con?guration 2 read/write 0x000c_060c ba 1 byte 1 byte alternate os visible parameters 1 read/write 0x04 bb 1 byte 1 byte alternate os visible parameters 2 read/write 0x00 c0 1 byte 1 byte error enabling 1 read/write 0x01 c1 1 byte 1 byte error detection 1 read/bit-reset 0x00 c3 1 byte 1 byte 60x bus error status read/bit-reset 0x00 c4 1 byte 1 byte error enabling 2 read/write 0x00 c5 1 byte 1 byte error detection 2 read/bit-reset 0x00 c7 1 byte 1 byte pci bus error status read/bit-reset 0x00 c8Ccb 4 byte 4 bytes 60x/pci error address read 0x00 f0 4 bytes 1, 2, or 4 bytes memory control con?guration 1 read/write 0xff n 2_0000 f4 4 bytes 1, 2, or 4 bytes memory control con?guration 2 read/write 0x0000_0003 f8 4 bytes 1, 2, or 4 bytes memory control con?guration 3 read/write 0x0000_0000 fc 4 bytes 1, 2, or 4 bytes memory control con?guration 4 read/write 0x0010_0000 table 10. MPC105 configuration registers (continued) address offset register size program accessible size register register access reset value
MPC105 pci bridge/memory controller technical summary 23 figure 3. MPC105 configuration space reserved device id (0x0001) vendor id (0x1057) pci status pci command class code standard programming subclass code revision id bist control latency timer header type cache line size max gnt interrupt pin min gnt interrupt line subordinate bus number disconnect counter bus number special cycle address power management configuration memory starting address memory starting address memory ending address memory ending address memory enable processor interface configuration 1 processor interface configuration 2 alternate os visible params 2 alternate os visible params 1 60x bus error status error detection 1 error enabling 1 60x/pci error address memory control configuration 1 memory control configuration 2 memory control configuration 3 memory control configuration 4 00 04 08 0c 3c 40 44 70 80 84 90 94 a0 a4 a8 ac b8 bc c0 c8 pci bus error status error detection 2 error enabling 2 c4 f0 f4 f8 fc / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / address offset extended memory starting address extended memory starting address 88 8c extended memory ending address extended memory ending address 98 9c
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